1. Field of the Invention
The present invention relates to an integrated circuit device, and more particularly, to a merged memory-logic integrated circuit device including a DRAM cell array and a logic circuit.
2. Description of the Related Art
With advances in semiconductor technology, semiconductor devices of the integrated circuit type have been developed, and such integrated circuit devices include, for example, a memory cell array and a logic circuit merged into a single semiconductor device. These integrated circuit devices are referred to as merged memory-logic integrated circuit devices. After a wafer including a plurality of merged memory-logic integrated circuit devices is manufactured, a wafer sort test process is carried out on each of the merged memory-logic integrated circuit devices to test their operation. During the wafer sort test process, testing of the memory cell arrays and logic portions is performed separately. More particularly, one test is performed to determine whether the logic portions operate correctly, and in separate operations the memory cell arrays are tested several times to check their characteristics both before and after repairing the memory cell arrays. During the wafer sort test process, probe tips, which are attached to a probe card to connect a test equipment to the wafer, are placed in contact with a plurality of pads included in a merged memory-logic integrated circuit device. That is, a plurality of pads are probed. Since memory cell arrays are tested several times, the time required to test the memory cell arrays is significant. To minimize the amount of the test time, a plurality of chips are simultaneously tested. In simultaneously probing a plurality of chips, the contact force of the probe tip, as well as the narrow distance between probes can cause problems as a plurality of tests are carried out.
To solve the problems, the distance between probe tips has been increased and the thickness of each probe tip has been increased. A pad, which has been probed, may be damaged which will reduce the strength of the bond between the bond wire and the pad. Therefore, as probe thickness increases, pad area must also increases. To solve the problem of the reduced adhesive strength, U.S. Pat. No. 5,506,499 describes a method of forming and using separate, auxiliary pads between primary pads. During testing of a merged memory-logic integrated circuit device, only the auxiliary pads are probed to test a memory cell array and, after the memory cell array is completely tested, wires are bonded to the primary pads, which have not been probed, and thus have not been damaged from the probing, thereby improving the strength of the bonds to the primary pads.
When the number of primary logic pads is small, forming auxiliary pads between the primary logic pads poses no problem. However, when the number of primary logic pads is large, forming auxiliary pads between the primary logic pads results in undesirable increase of the size of a merged memory-logic integrated circuit device. As the sizes of merged memory-logic integrated circuit devices increase, the production costs are increased.
To solve the above problems, the present invention provides an integrated circuit device having bonding pads which maintain reliable bonding even after multiple probing during a wafer sort test process.
In accordance with one embodiment of the present invention, an integrated circuit device is provided which comprises: a pad electrically connected to the circuitry of the integrated circuit device, wherein the pad comprises: a probing portion to which probe tips are brought into contact for transmission of a test signal to the circuitry of the integrated circuit device; and a bonding portion for providing electrical connection to the circuitry of the integrated circuit device.
In another embodiment of the present invention, an integrated circuit device is provided which includes a substrate having a memory cell array and a logic circuit, with the integrated circuit device comprising: a logic pad positioned on a surface of said substrate; a test pad positioned on a surface of said substrate; a multiplexer electrically connected to the logic pad, the test pad, the memory cell array and logic circuit, the multiplexer being adapted to receiver control signal having first and second states, said multiplexer responding to receipt of a control signal of said first state to couple the logic pad to the logic circuit, and said multiplexer responding to receipt of a control signal of said second state to couple the test pad to the memory cell array; and a resistor connected to the test pad.
In the integrated circuit of the immediately preceding embodiment, the logic pad comprises a metal layer having a portion positioned above a surface of the substrate, the portion having an area; and wherein said device further includes a conductive line connecting the test pad to the multiplexer, and further wherein a portion of said conductive line is positioned within the area.
In accordance with a further embodiment of the present invention, an integrated circuit device having a memory cell array and a logic circuit is provided, and the integrated circuit device comprises: a logic pad; a test pad; transmitting means electrically connected to the test pad, said transmitting means including an input for receiving a control signal, and said transmitting means including an output for providing thereat a signal received from the test pad when the control signal is activated; and a multiplexer electrically connected to the logic pad, to the transmitting means, to the memory cell array and to the logic circuit, said multiplexer including an input for receiving the control signal, said multiplexer being responsive to receipt of the control signal to transmit a signal received from the logic pad to the logic circuit, and to transmit a signal received from the test pad to the memory cell.
In another embodiment of the invention, a method of manufacturing and testing an integrated circuit device is provided, with the method comprising: providing a pad having a bonding portion and a probing portion; electrically connecting the pad to circuitry of said integrated circuit device; and testing the operation of the electrical circuitry connected to the pad by bringing a probe into contact with only the probing portion of the pad and applying electrical signals to the probe.
According to another embodiment, an integrated circuit device having a memory cell array and a logic circuit is provided, where the integrated circuit device comprises: a first pad electrically connected to the logic circuit; and a second pad electrically connected to the memory cell array and the logic circuit, wherein the second pad comprises: a probing portion to which probe tips are brought into contact for transmission of a test signal for testing the integrated circuit device; and a bonding portion for providing electrical connection to an external system.